Related Patent Applications
The invention disclosed herein is related to the U.S. patent application Ser. No. 07/864,112, filed Apr. 6, 1992, entitled "Massively Parallel Array Processor", by G. G. Pechanek, et al., assigned to the IBM Corporation and incorporated herein by reference.
The invention disclosed herein is also related to the U.S. patent application by G. G. Pechanek, et al. which is entitled "DISTRIBUTED CONTROL PIPELINE WITH JOINT PE/SEQUENCER CONTROL", Ser. No. 08/365,858, filed Dec. 29, 1994, assigned to the International Business Machines Corporation, and incorporated herein by reference.
The invention disclosed herein is also related to the U.S. Pat. Application by G. G. Pechanek, et al. which is entitled "ARRAY PROCESSOR TOPOLOGY RECONFIGURATION SYSTEM AND METHOD", Ser. No. 08/366,140, filed Dec. 29, 1994, assigned to the International Business Machines Corporation, and incorporated herein by reference.
The invention disclosed herein is also related to the U.S. patent application by G. G. Pechanek, et al. which is entitled "PARALLEL PROCESSING SYSTEM AND METHOD USING SURROGATE INSTRUCTIONS", Ser. No. 08/373,128, filed Jan. 17, 1995, assigned to the International Business Machines Corporation, and incorporated herein by reference.
Communications in an instruction-driven programmable parallel processing system typically possesses an inherent latency in communicating between the processing elements. Communication instructions and communications between buffering memories are standard approaches for interfacing between processing elements. All these approaches possess an inherent latency which must be accounted for before data can be further processed. This degrades the potential performance that a parallel processing system can achieve.